1. Field of the Invention
This invention relates to methods of forming integrated dielectric layers which may be used in semiconductor devices, and particularly relates to methods that involve formation of etch-stop layers using a CVD apparatus.
2. Description of the Related Art
Semiconductor devices include metal layers that are insulated from each other by dielectric layers. As device features shrink, a reduction of the distance between the metal layers increases. To achieve this task, a low dielectric film is introduced to replace the conventional silicon dioxide films and other materials having a relatively high dielectric constant to form a dielectric layer that separates the metal lines, i.e., metal layers.
A material that may be considered suitable for such a task includes a carbon-doped silicon dioxide film. Using this material to divide the metal lines may yield a device having a reduced propagation delay, cross-talk noise, and power dissipation. Although this film appears to be perfect for replacing silicon dioxide films, there are other film properties that may not be comparable to silicon dioxide films. That includes, for instance, elastic modulus and hardness. Most carbon-doped films have less than 14% of silicon dioxide elastic modulus and 20% of silicon dioxide hardness. These may lead to a severe problem when the wafer is subjected to subsequent processes such as chemical mechanical polishing (CMP) and packaging involving long-standing integration issues.
Accordingly, there is a need for films having high modulus and hardness to circumvent the long-standing integration issues. The conventional schemes of so called xe2x80x9cno etch-stop integrationxe2x80x9d have not been very successful due to the occurrence of strong attack on the corners of via holes during a subsequent metal trench etch process.
Various damascene methods have been reported in the field of microelectronic fabrication for forming within microelectronic fabrications damascene structures with desirable properties. For example, the damascene methods include, but are not limited to, the damascene methods disclosed in the following, the disclosure of which is incorporated herein by reference in its entirety:
(1) U.S. Pat. No. 6,100,184 to Zhao et al., teaching a dual damascene method for forming a copper-containing contiguous patterned conductor interconnect and a patterned conductor stud layer within a corresponding trench contiguous with a corresponding via formed through a dielectric layer formed with a comparatively low dielectric constant dielectric material, thereby contacting a copper-containing conductor layer formed thereunder, wherein a conductor barrier/etch-stop layer is used to selectively passivate only the top surface of the copper-containing conductor layer formed thereunder;
(2) U.S. Pat. No. 6,140,226 Zhao et al. teaching a dual damascene method for forming a contiguous patterned conductor interconnect and a patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer formed with a comparatively low dielectric constant dielectric material wherein a sidewall liner layer is used for the purposes of protecting a sidewall of the trench from lateral etching when contiguously forming the via therewith;
(3) U.S. Pat. No. 6,177,364 to Huang teaching a dual damascene method for forming a contiguous patterned conductor interconnect and a patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer formed with a comparatively low dielectric constant fluorosilicate glass (FSG) dielectric material wherein a hydrogen-nitrogen plasma treatment is employed for the purposes of passivating a sidewall surface of the dielectric layer within the corresponding trench contiguous with the corresponding via prior to forming therein the contiguous patterned conductor interconnect and patterned conductor stud layer; and
(4) U.S. Pat. No. 6,211,092 to Tang et al. teaching a counterbore type dielectric etch method which may be employed when forming through a dielectric layer a dual damascene aperture for a dual damascene method, wherein the counterbore type dielectric etch method uses a plurality of etch steps when first forming a via through the dielectric layer.
In the field of microelectronic fabrication, desirable are additional damascene methods and materials which can be employed for providing patterned microelectronic conductor layers each interposed between microelectronic dielectric layers formed with comparatively low dielectric constant dielectric materials, thereby attenuating damage to the microelectronic dielectric layers.
All low-dielectric constant films that are currently available on the market are manufactured accordingly and have an elastic modulus of lower than 10 GPa as measured by Diamond indentation methods (e.g., by a Nano-indenter manufactured by MTS).
An object of the present invention is to provide a method and a film having great advantages over the conventional methods and films with respect to subsequent processes such as CMP and Packaging.
The conventional integration methods are further explained below. In implementing conventional dual damascene techniques wherein a via is formed before a trench, an etch-stop layer is formed on and under a first dielectric layer which overlies a capped metal feature. The etch-stop layer is typically formed with silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, which is chosen for its high etch selectivity with respect to an overlying second dielectric layer which is then deposited on the etch-stop layer. Thus, the second dielectric layer is deposited on the upper etch-stop layer. A photoresist mask is then formed over the second dielectric layer, and anisotropic etching is conducted to form a via through the first and second dielectric layers and stops on the lower etch-stop layer. Subsequently, a trench pattern is formed on the second dielectric with a barrier anti-reflective coating (BARC) filling the via (Conformal and Planarization). Trench anisotropic etching is conducted to form a trench and stops on the upper etch-stop layer (which is under, the second dielectric layer and thus is referred to as an xe2x80x9cintermediatexe2x80x9d etch-stop layer). Finally, the photoresist is removed with a conventional ashing process, and then copper metallization is commenced.
As miniaturization proceeds apace with attendant shrinkage in the size of metal lines, e.g., the width of a metal line is about 0.25 micron or lower, or about 0.1 micron or lower, the ILD dielectric constant of the interlining material is very important. This includes the dielectric constant of the etch-stop layer. Accordingly, there is the need for an interconnection methodology enabling the formation of metal features, such as metal lines, with high dimensional accuracy and low effective k-value.
The present invention provides solutions to these complicated integration problems.
In an aspect of the present invention, a method is provided to form on a substrate a laminated structure including a layer-to-be-etched and an etch-stop layer. In an embodiment, the method comprises the steps of: (i) introducing into a reactor a reaction gas comprised of a source gas containing silicon and carbon at a source gas flow rate and an inert gas at an inert gas flow rate which is 40% or higher of the source gas flow rate; (ii) applying plasma energy to a space where the reaction gas is present upstream of a substrate mounted on a heated substrate-supporting member; (iii) forming an etch-stop layer on the substrate from the reaction gas with plasma energy; and (iv) forming a laminated structure by forming at least one layer-to-be-etched on the substrate. In the above, the laminated structure may be a dual damascene structure.
The source gas may be Sixcex1Oxcex1xe2x88x921R2xcex1xe2x88x92xcex2+2(OCnH2n+1) wherein xcex1 is an integer of 1-3, xcex2 is an integer of 1-3, n is an integer of 1-3, and R is C1-6 hydrocarbon attached to Si. In a preferred embodiment, the source gas is dimethyl-dimethoxy silane.
According to the above embodiment of the prevent invention, the etch-stop layer can be formed by changing the inert gas flow rate, the step of forming the etch-stop layer and the step of forming the layer-to-be-etched can continuously be conducted in the same chamber without breaking a vacuum. This may be a great advantage to semiconductor device manufacturing. Further, the step of forming the etch-stop layer and the step of forming the layer-to-be-etched can use the same source gas and inert gas.
When the inert gas flow rate is high, the density of the resulting film becomes high, i.e., exhibiting excellent hardness and resistance to etching treatment. Thus, the inert gas flow rate in the step of forming the etch-stop layer may be higher than in the step of forming the layer-to-be-etched. Further, in the step of forming the layer-to-be-etched, the inert gas flow rate may be no more than 40% of the source gas flow rate, so that two films having different characteristics can easily be produced. The layer-to-be-etched may serve as an insulator and the etch-stop layer may serve as a mask, and thus, the step of forming the etch-stop layer may be conducted under conditions to adjust a dielectric constant of the etch-stop layer to 3.0 or lower.
In an embodiment, the plasma energy may be applied between a showerhead and a susceptor, which serve as upper and lower electrodes, respectively, wherein the substrate is mounted on the susceptor. Further, the reaction gas may be excited with plasma energy in a remote plasma chamber prior to the step of introducing the reaction gas into the reactor.
The source gas flow rate may be in the range of 50 sccm to 200 sccm in an embodiment.
The method may further comprise etching the layer-to-be-etched except for the etch-stop layer to form a hole, and filling the hole with copper.
In another aspect of the present invention, a method of dielectric film integration is provided. In an embodiment, the method comprises the steps of: (i) depositing a first dielectric layer on a substrate using a first reaction gas comprised of a source gas containing Si, C, O, and H at a first source gas flow rate and an inert gas at a first inert gas flow rate, wherein the first inert gas flow rate is no more than 40% of the first source gas flow rate, said first reaction gas being excited with plasma energy; and (ii) continuously depositing a second dielectric layer on top of the first dielectric layer using a second reaction gas comprised of a source gas containing Si, C, O, and H at a second source gas flow rate and a second inert gas at a second inert gas flow rate, wherein the second inert gas flow rate is 40% or higher of the second source gas flow rate, said second reaction gas being excited with plasma energy. In the above, the source gas may be an alkyl organic silicate. Further, the first and second dielectric layers may be made of carbon-doped silicon oxide in an embodiment.
The first dielectric layer can serve as an inter metal dielectric (IMD) layer. The second dielectric layer can serve as an IMD etch stop layer or a chemical mechanical polishing (CMP) cap layer.
According to the above embodiments, the first and second dielectric layers can have a modulus of 12 GPa or lower and 13 GPa or higher, respectively. Further, the first and second dielectric layers can have a hardness of 2.0 GPa or lower and 2.0 GPa or higher. Thus, the first and second dielectric layers may effectively serve as an insulator and an etch stopper, respectively.
The dielectric layers may have an amorphous structure wherein the Si of Sixe2x80x94O as C bonded thereto, which C has H bonded thereto.
As with the first aspect of the present invention, the step of forming the first dielectric layer and the step of forming the second dielectric layer may continuously be conducted in the same chamber without breaking a vacuum or at least without unloading the substrate from a reactor. In an embodiment, the method may be conducted in a CVD chamber. Further, the step of forming the first dielectric layer and the step of forming the second dielectric layer may use the same source gas and inert gas. The first and second source gas flow rates may also be independently in the range of 50 sccm to 200 sccm. The step of forming the second dielectric layer may be conducted under conditions to adjust a dielectric constant of said layer to 3.0 or lower.
In another embodiment, the first and second reaction gases may be first excited with plasma energy in a remote plasma chamber disposed upstream of a reactor where the substrate is processed.
For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
Further aspects, features and advantages of this invention will become apparent from the detailed description of the preferred embodiments which follow.